Video Entertainment System
Channel F introduces a new era in video entertainment. The first cartridge game system. High-performance entertainment you can change—for a new challenge, new action anytime.
Co-designed by pioneering black electronics engineer Jerry Lawson, the Channel F (originally the Video Entertainment System) was the first videogame console to use interchangeable ROM cartridges. Fairchild ultimately produced twenty-six of these yellow “Videocarts,” which drew inspiration from 8-track tape cartridges and used a sequential numbering system. Among its design innovations were the hardware Hold (pause) button, integrated controller storage, front-loading cartridge mechanism, and unique “plunger” hand controls. The Channel F debuted in November 1976 for $149.95, inaugurating the so-called “second generation” of home videogame consoles.
|CPU||Fairchild F8 (1.79MHz)|
|RAM||64 bytes (scratchpad registers) / 2KB|
|Resolution||128x64 (VRAM) | 102x58 (visible)|
|Sound||120Hz, 500Hz, and 1kHz beeps System I: built-in speaker (no volume control) System II: audio to TV via RF|
|Input||Two hardwired Hand-Controllers, 5 console buttons (Reset, Time, Mode, Hold, Start)|
|Media||Videocarts (i.e., cartridges)|
Grandstand Video Entertainment Computer (Great Britain, 1976)
The VES wiki is the most comprehensive and up-to-date repository of Fairchild VES programming resources. The wiki includes detailed hardware specifications, programming info, a downloadable “Development Pack,” disassemblies of commercial ROMs, and a comprehensive homebrew list.
Sean Riddle's F8 Info site provides links to the F8Tool assembler/disassembler, source code to his Lights Out (2004) homebrew and Peter Trauner's port of Tetris, disassemblies for the BIOS and two Videocarts, and build instructions for the Channel F MultiGame, a multi-cart.
For chiptune musicians, there is Sleizsa, a “low level sequencer for the Channel F microchip, created by B00daw in 2008.”
Fairchild Channel F software is programmed in F8 microprocessor assembly.
The Fairchild F8 Microprocessor comprises multiple chips: the F3850 CPU, F3851 Programmable Storage Unit (PSU), F3852 Dynamic Memory Interface (DMI), F3853 Static Memory Interface (SMI), and the F3854 Direct Memory Access (DMA).
The F3850 CPU contains an 8-bit Accumulator, a 5-bit Status Register (W), a 6-bit Indirect Scratchpad Address Register (ISAR), and 64 8-bit scratchpad that may be used as general-purpose RAM (accessible via the ISAR). Selected scratchpad registers are reserved for direct communication with other registers within the F8 system—register 9 (J) is temporary storage for the CPU status regsiter (W), while registers 10—15 (H, K, and Q) communicate directly with data and program memory address registers that are maintained on the F3851, F3852, and F3853 chips.
The PSU contains read-only memory for storing the program instructions. It also maintains the program counter (PC0), stack register (PC1), and data counter (DC). The DMI provides the 16 address lines and control signals necessary to interface standard memory circuits—either static or dynamic—to an F8 system. The SMI provides the necessary address lines and control signals to operate standard static RAM circuits. Finally, DMA provides a high-speed data path between F8 memory and, e.g., a high-speed peripheral.
The F8 instruction set includes “more than 70 instructions” and operates on 8-bit units of information.